In many memory devices, flexibility is added through the use different modes of operation in which the memory device can operate. Through the use of different operating modes, the memory device can perform operations or functions not typically desired by a user, but provide additional capabilities that may found desirable by memory device designers and manufacturers. For example, one popular mode of operation is the non-user test mode which provides additional test functionality that facilitates the testing of the memory devices.
There are many well known approaches to invoking the different modes of operation of a memory device. For example, entry into the test modes is often made by way of applying a relatively high-voltage signal to an input pin or pins of the memory device. The point at which the test mode is invoked, that is, the trigger voltage, is typically measured relative to a voltage source, such as the device supply voltage VCC or the input/output supply voltage VCCQ. Shown in FIG. 1 is a typical arrangement of circuitry 100 that is used to determine if a test mode has been invoked through the application of a relatively high-voltage to a device input pad, and in response, generate an output signal having a voltage level indicative of whether the test mode should be entered. The circuitry 100 includes a high-voltage detector 110 to which a reference voltage 112 and an input signal 114 are applied. As illustrated in FIG. 1, the reference voltage 112 is the device supply voltage VCC and the input signal 114 is an input signal PAD from a device input pad. The HV detector 110 compares the voltage of the PAD signal to VCC or a voltage level related to VCC, and in response, produces a test enable signal TEST_EN having a voltage indicating whether the test mode should be entered. The TEST_EN signal can then be used to place the device into a test mode. The design and implementation of HV detectors, such as the HV detector 110, are known in the art.
A problem with previously discussed approach of test mode entry, however, is that noisy signals or dramatic voltage variations in the signals applied to input pads of a memory device may inadvertently trigger entry into a test mode. Operation of the memory device after accidentally entering into such a mode by a user could irreparably damage the part. Consequently, the test mode entry voltage should be set high enough to avoid inadvertent test mode entry.
Further complicating the issue, however, is the fact that it may be desirable for the test mode entry voltage to be lower than that which will ensure a test mode is not inadvertently entered, such as in the following case. In order to increase test throughput, memory devices, test programs, and test equipment have been designed to perform device testing more efficiently. For example, memory devices have been designed to test multiple blocks of memory in parallel, thus avoiding the testing of memory cells one at a time. Additionally, test programs have been written to take advantage of the parallel testing capabilities provided by the memory devices, and test equipment have been modified to increase the number of devices that can be tested concurrently by the test equipment. However, the number of devices that can be tested concurrently may be limited by test equipment limitations. For example, memory testers typically have limited high-voltage drive capabilities. Thus, where high-voltage signals are applied during testing, the number of devices that can be tested concurrently will be limited. In the particular case where the high-voltage drive capabilities of the test equipment is limited, the test entry voltage should be reduced to accommodate this limitation. However, with the conventional high-voltage detection circuitry previously discussed with respect to FIG. 1, where the test mode entry voltage is based on one voltage, such as VCC, lowering the mode trigger voltage increases the likelihood that test mode will be entered inadvertently.
Additionally, many memory devices are designed to operate over a range of power supply voltages. In some cases, the device supply voltage and the input/output supply voltage can be at different voltage levels. Where this is the case, having the test mode entry voltage level based on one voltage, such as the device supply voltage, may significantly reduce the margin between the acceptable voltage levels of input signals and the test mode trigger voltage.
An approach to decreasing the likelihood of inadvertently entering a test mode, where entry is made through the application of high-voltage signals, is provided in U.S. Pat. No. 5,526,364 to Roohparvar. As described therein, high-voltage signals are applied to two or more input pins of the memory device to enter into a test mode. However, as previously discussed, where the test equipment has limited high-voltage drive capability, driving multiple pins to sufficient voltage levels to enter into the test modes will reduce the number of devices that can be tested concurrently. Thus, the approach described in the aforementioned patent may not provide an acceptable alternative.
Therefore, there is a need for an alternative apparatus and method that can be used to generate test mode entry signals in response to an input signal.